Frontend Design and Verification Reference Flows

Reference Flow Architecture

Overview

The Frontend Design and Verification Reference Flows provide a comprehensive, standardized methodology for RTL development, verification, and quality assurance. These reference flows establish best practices for project organization, file management, build processes, and verification workflows.

Integrated with the EDAUtils AI System, these flows enable automated quality checks, intelligent tool selection, and continuous improvement through machine learning feedback loops.

Key Flow Components

Standard Directory Structure - Organized hierarchy for design and verification files
Multiple Design Configuration Support - Parameter-based RTL variants
Automated File List Generation - Dynamic compilation of source files
RTL Compile and Elaboration - Using Anvil/Anvhier tools
Simulation Flow - Icarus Verilog integration
Linting and Quality Checks - Verilator-based analysis
Synthesis Flow - Yosys integration for ASIC/FPGA
Equivalence Checking - Formal verification of transformations
DV Build System - Automated testbench compilation
Regression Framework - Parallel test execution
Coverage Collection - Functional and code coverage
IPQC Integration - Automated quality checks

Design Flow Details

1. Project Setup: Initialize flow root, EDA tool versions, and environment variables. Set up workspace with proper permissions and paths.

2. Directory Structure: Create standard hierarchy following OpenCores guidelines - separate folders for RTL, docs, verification, synthesis, and scripts.

3. Design Configuration: Support multiple design variants through parameter files. Generic RTL with +define+ macros and parameter overrides (e.g., addr=128, data=64).

4. File List Generation: Automated generation of consolidated, flattened file lists including SIP/HIP dependencies. Handles include paths, defines, and library mappings.

5. RTL Compilation: Anvil/Anvhier for syntax checking and elaboration. Validates module hierarchies and parameter propagation.

6. Synthesis: Yosys-based synthesis with liberty library constraints. Technology mapping for ASIC or FPGA targets.

Design Verification (DV) Flow

DV Environment Setup: Initialize DV flow root with simulator version, VIP installations, and test environment configuration.

DV Directory Structure: Separate directories for testbenches, tests, VIPs, coverage, and results. Follows UVM/OVM standards where applicable.

VIP Management: List and install verification IP dependencies. Support for standard protocol VIPs (AXI, AHB, APB, etc.).

Build Flow: Compile testbench and design together. Generate simulation executable (a.out/simv) with proper elaboration options.

Regression Execution: Parallel test execution with configurable seeds and options. Each test runs with specific command-line arguments.

Analysis and Reporting: Automated log parsing, error detection, coverage merging, and dashboard generation. Trend analysis across regression runs.

Integration with EDAUtils AI System

Flow Inputs

Standard inputs for reference flows:

RTL source files (Verilog/SystemVerilog)
Design configuration parameters
Synthesis constraints (SDC)
Testbenches and verification plans
VIP dependencies and configurations
Coverage requirements

Flow Outputs

Generated artifacts and reports:

Compiled simulation executables
Synthesis netlists and reports
Lint and quality check reports
Regression test results
Coverage databases and reports
IPQC quality metrics

Supported EDA Tools

Anvil/Anvhier - RTL compile and elaboration
Icarus Verilog - Open-source simulation
Verilator - Fast linting and simulation
Yosys - Open-source synthesis
VCS/Xcelium - Commercial simulators (optional)
Design Compiler - Commercial synthesis (optional)
Baya - SoC integration and RTL generation

Explore Individual Flows

🎨 Design Flows

Complete RTL development methodology including:

Project Setup & Configuration
File List Generation
RTL Compile & Elaborate
Linting & Quality Checks
Synthesis & Equivalence

View Design Flows

✅ Verification Flows

Comprehensive DV framework including:

DV Environment Setup
VIP Management
Build & Compile
Test Execution & Regression
Coverage & Reporting

View Verification Flows

Library of EDA Utilities